Paste: two input generic synchronized adder

library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std.all ;

entity synchronized_adder is
  generic ( 
    A_DELAY :       positive            := 10 ;
    B_DELAY :       positive            := 3
  ) ;
  port (
    clock   :   in  std_logic ;
    a       :   in  signed(15 downto 0) ;
    b       :   in  signed(15 downto 0) ;
    c       :   out signed(15 downto 0)
  ) ;
end entity ; -- synchronized_adder

architecture arch of synchronized_adder is

    type delay_t is array(N downto 1) of signed(a'range) ;
    
    signal delay : delay_t := (others =>(others =>'0')) ;
    
    signal delay_in : signed(15 downto 0) ;

begin
    
    delay_in <= a when A_DELAY < B_DELAY else b ;
    
    perform_delay : process( clock )
    begin
        if( rising_edge( clock ) ) then
            delay <= delay(N-1 downto 2) & delay_in ;
        end if ;
    end process ; -- perform_delay
    
    perform_addition : process( clock )
    begin
        if( rising_edge( clock ) ) then
            if( A_DELAY < B_DELAY ) then
                c <= delay(N) + b ;
            else
                c <= delay(N) + a ;
            end if ;
        end if ;
    end process ; -- perform_addition

end architecture ; -- arch