Paste: delay example

-- Package declaration of your constant and your component
library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std.all ;

package operation1_p is
    
    constant OPERATION1_DELAY : positive := 12 ;
    
    component operation1 is
      port (
        clock   :   in  std_logic ;
        a       :   in  signed(15 downto 0) ;
        b       :   in  signed(15 downto 0) ;
        c       :   out signed(15 downto 0)
      ) ;    
    end component ;
    
end package ; -- operation1_p

-- Entity and architecture of your operation
library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std.all ;

entity operation1 is
  port (
    clock   :   in  std_logic ;
    a       :   in  signed(15 downto 0) ;
    b       :   in  signed(15 downto 0) ;
    c       :   out signed(15 downto 0)
  ) ;
end entity ; -- operation1

architecture arch of operation1 is

    -- Stuff goes in here ...

begin

    -- More stuff in here ...

end architecture ; -- arch

-- Instantiation
library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std.all ;

library work ;
    use work.operation1_p.all ;
    use work.operation2_p.all ;

entity instantiation is
  port (
    clock   :   in  std_logic ;
    a       :   in  signed(15 downto 0) ;
    b       :   in  signed(15 downto 0) ;
    c       :   in  signed(15 downto 0) ;
    d       :   in  signed(15 downto 0) ;
    e       :   out signed(15 downto 0)
  ) ;
end entity ; -- instantiation

architecture arch of instantiation is
    
    -- Appropriate signal names here
    
begin
    
    U_op1 : operation1
      port map (
        clock   =>  clock,
        a       =>  op1_a,
        b       =>  op1_b,
        c       =>  op1_c
      ) ;
      
    U_op2 : operation2
      port map (
        clock   =>  clock,
        a       =>  op2_a,
        b       =>  op2_b,
        c       =>  op2_c
      ) ;
      
    U_synchronized_adder : synchronized_adder
      generic map (
        N       =>  (OPERATION1_DELAY - OPERATION2_DELAY)
      ) port map (
        clock   =>  clock,
        a       =>  op1_c,
        b       =>  op2_c,
        c       =>  synch_c
      ) ;
    
end architecture ; -- arch