Author: | foo |
---|---|
Mode: | verilog |
Date: | Fri, 29 Apr 2011 03:21:06 |
module jk_flip_flop ( input clk, input j, input k, output reg q ); always @(posedge clk) case ({j,k}) 2'b11 : q <= ~q; // toggle. 2'b01 : q <= 1'b0; // reset. 2'b10 : q <= 1'b1; // set. 2'b00 : q <= q; // hold. endcase endmodule