##inc-d -1 ##peek RAX D 0 ##slot-imm RCX RAX 2 7 ##slot-imm RCX RCX 2 7 ##slot-imm RAX RAX 3 7 ##slot-imm RAX RAX 2 7 ##peek RDX D -1 ##slot-imm RBX RDX 2 7 ##slot-imm RBX RBX 2 7 ##slot-imm RDX RDX 3 7 ##slot-imm RDX RDX 2 7 ##load-memory-imm XMM0 RCX 7 double-2-rep f ##load-memory-imm XMM1 RAX 7 double-2-rep f ##load-memory-imm XMM2 RDX 7 double-2-rep f ##load-memory-imm XMM3 RBX 7 double-2-rep f ##allot RCX 32 byte-array RAX ##shuffle-vector-halves-imm XMM4 XMM0 XMM1 { 1 0 } double-2-rep ##shuffle-vector-halves-imm XMM5 XMM2 XMM3 { 0 0 } double-2-rep ##mul-vector XMM4 XMM4 XMM5 double-2-rep ##shuffle-vector-halves-imm XMM1 XMM1 XMM0 { 0 0 } double-2-rep ##shuffle-vector-halves-imm XMM5 XMM3 XMM2 { 1 0 } double-2-rep ##mul-vector XMM1 XMM1 XMM5 double-2-rep ##sub-vector XMM4 XMM4 XMM1 double-2-rep ##store-memory-imm XMM4 RCX 7 double-2-rep f ##load-reference RAX { double-2 1 2 tuple 3547099654 simd-128 -91419929541750015 double-2 -91419085198784861 } ##allot RDX 24 tuple RBX ##set-slot-imm RAX RDX 1 7 ##load-tagged RBX 256 ##set-slot-imm RBX RCX 1 9 ##set-slot-imm RCX RDX 2 7 ##allot RCX 32 byte-array RBX ##shuffle-vector-imm XMM1 XMM0 { 0 0 } double-2-rep ##shuffle-vector-imm XMM2 XMM3 { 1 0 } double-2-rep ##mul-vector XMM1 XMM1 XMM2 double-2-rep ##shuffle-vector-imm XMM0 XMM0 { 1 0 } double-2-rep ##shuffle-vector-imm XMM3 XMM3 { 0 0 } double-2-rep ##mul-vector XMM0 XMM0 XMM3 double-2-rep ##sub-vector XMM1 XMM1 XMM0 double-2-rep ##store-memory-imm XMM1 RCX 7 double-2-rep f ##allot RBP 24 tuple RBX ##set-slot-imm RAX RBP 1 7 ##load-tagged RAX 256 ##set-slot-imm RAX RCX 1 9 ##set-slot-imm RCX RBP 2 7 ##allot RCX 32 tuple RAX ##load-reference RAX { double-4 2 1 tuple 3547099654 double-4 -135291120707467030 } ##set-slot-imm RAX RCX 1 7 ##set-slot-imm RDX RCX 2 7 ##set-slot-imm RBP RCX 3 7 ##replace RCX D 0 ##branch