library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; entity synchronized_adder is generic ( N : positive := 5 ) ; port ( clock : in std_logic ; a : in signed(15 downto 0) ; b : in signed(15 downto 0) ; c : out signed(15 downto 0) ) ; end entity ; -- synchronized_adder architecture arch of synchronized_adder is type delay_t is array(N downto 1) of signed(a'range) ; signal delay : delay_t := (others =>(others =>'0')) ; begin perform_delay : process( clock ) begin if( rising_edge( clock ) ) then delay <= delay(N-1 downto 2) & a ; end if ; end process ; -- perform_delay perform_addition : process( clock ) begin if( rising_edge( clock ) ) then c <= delay(N) + b ; end if ; end process ; -- perform_addition end architecture ; -- arch